Deli Counter Display
Project Overview
The purpose of this project was to create a circuit in Multisim that could count up to 80 then reset utilizing a SSI and MSI counter in sequence.
Final Project Conclusions
Small scale integration uses multiple flip flops in sequence while MSI uses 4 pre-wired flip flops in series.
The limitations of the MSI circuit that I created is that it could only function as an up counter and that it had to start at zero.
The ripple effect is flickering of the display due to signal delay in the circuit.
Anthony had a different circuit than I did and it was different because he utilized transistors in his design.
When I start the simulation the clock sends a signal through the MSI chips making it count 0-9 then reset repeatedly. Once 9 is reached a signal is sent to the SSI chips making it count 0-8 every time a signal is sent. The count is limited in this circuit by using logic, 4 input NAND gates, to control the load and detection number, which is one higher then number shown. Once the numbers on both displays reach 80 the simulation will pause. The simulation is paused at 80 because the detection of an 8 in the SSI sends a signal to the MSI to stop, thus pausing the simulation. The additional NAND and AND gates are used to wire the two circuits off of a single reset button and it also is what’s used to limit the counts of both. Once 80 is reached then the reset switch is hit setting the circuit back to 0. Also, the circuit can be reset with the switch at any point, not just 80. The reset works by powering the clear in the MSI chip and the clears in each flip flop in the SSI.
The difference between PLD and Design mode is what is done with it after completion. PLD is used once completed by downloading it to a chip and putting it in a board. This is done by assigning the pins of the chip in the simulation to inputs and outputs. The difference between the input and output connectors is mainly in the simulator but the distinctive difference is needed so the circuit works. Once all components are assembled and connected the program is downloaded to the chip which takes about 2 minutes and then is installed in the breadboard.
The limitations of the MSI circuit that I created is that it could only function as an up counter and that it had to start at zero.
The ripple effect is flickering of the display due to signal delay in the circuit.
Anthony had a different circuit than I did and it was different because he utilized transistors in his design.
When I start the simulation the clock sends a signal through the MSI chips making it count 0-9 then reset repeatedly. Once 9 is reached a signal is sent to the SSI chips making it count 0-8 every time a signal is sent. The count is limited in this circuit by using logic, 4 input NAND gates, to control the load and detection number, which is one higher then number shown. Once the numbers on both displays reach 80 the simulation will pause. The simulation is paused at 80 because the detection of an 8 in the SSI sends a signal to the MSI to stop, thus pausing the simulation. The additional NAND and AND gates are used to wire the two circuits off of a single reset button and it also is what’s used to limit the counts of both. Once 80 is reached then the reset switch is hit setting the circuit back to 0. Also, the circuit can be reset with the switch at any point, not just 80. The reset works by powering the clear in the MSI chip and the clears in each flip flop in the SSI.
The difference between PLD and Design mode is what is done with it after completion. PLD is used once completed by downloading it to a chip and putting it in a board. This is done by assigning the pins of the chip in the simulation to inputs and outputs. The difference between the input and output connectors is mainly in the simulator but the distinctive difference is needed so the circuit works. Once all components are assembled and connected the program is downloaded to the chip which takes about 2 minutes and then is installed in the breadboard.